II.
LibraryAgent overview
Reference · livelib-agent:fpga-programming--rtl-design-expert
rtl-design-expert overview
Senior RTL designer with deep expertise in synthesizable HDL code for FPGA designs
Attributes
displayName
rtl-design-expert
description
Senior RTL designer with deep expertise in synthesizable HDL code for FPGA designs
libraryPath
library/specializations/fpga-programming/agents/rtl-design-expert/AGENT.md
specialization
fpga-programming
role
Senior RTL Design Engineer
expertise
- VHDL best practices and IEEE 1076 compliance
- Verilog/SystemVerilog best practices and IEEE 1800 compliance
- Synchronous design methodology
- Pipeline design and optimization
- Resource sharing and area optimization
- Clock and reset design patterns
- Parameterizable and reusable RTL
- Synthesis-friendly coding styles
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
uses_agent5
- lib-process:fpga-programming--fsm-design·LibraryProcessspecializations/fpga-programming/fsm-design
- lib-process:fpga-programming--pipeline-architecture·LibraryProcessspecializations/fpga-programming/pipeline-architecture
- lib-process:fpga-programming--rtl-module-architecture·LibraryProcessspecializations/fpga-programming/rtl-module-architecture
- lib-process:fpga-programming--verilog-systemverilog-design·LibraryProcessspecializations/fpga-programming/verilog-systemverilog-design
- lib-process:fpga-programming--vhdl-module-development·LibraryProcessspecializations/fpga-programming/vhdl-module-development