II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--verilog-systemverilog-design
specializations/fpga-programming/verilog-systemverilog-design overview
Verilog/SystemVerilog Design Implementation - Implement digital designs using Verilog or SystemVerilog following IEEE 1800 standards. Create parameterized modules with proper use of always_ff, always_comb, and interface constructs.
Attributes
displayName
specializations/fpga-programming/verilog-systemverilog-design
description
Verilog/SystemVerilog Design Implementation - Implement digital designs using Verilog or SystemVerilog
following IEEE 1800 standards. Create parameterized modules with proper use of always_ff, always_comb, and interface
constructs.
libraryPath
library/specializations/fpga-programming/verilog-systemverilog-design.js
specialization
fpga-programming
references
- - IEEE 1800-2023 SystemVerilog: https://standards.ieee.org/standard/1800-2023.html
- - Verilog IEEE 1364-2005: https://standards.ieee.org/standard/1364-2005.html
- - SystemVerilog for Design: https://www.veripool.org/verilator/
example
const result = await orchestrate('specializations/fpga-programming/verilog-systemverilog-design', {
moduleName: 'axi_stream_filter',
functionality: 'AXI-Stream data filter with configurable threshold',
language: 'SystemVerilog',
targetDevice: 'Intel Agilex',
interfaces: ['axi_stream_if.slave s_axis', 'axi_stream_if.master m_axis'],
parameters: ['DATA_WIDTH = 32', 'THRESHOLD = 128']
});
usesAgents
- rtl-design-expert
- verification-expert
- synthesis-expert
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:architecture-decision-record·WorkflowArchitecture Decision Record
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
uses_agent3
- lib-agent:fpga-programming--rtl-design-expert·LibraryAgentrtl-design-expert
- lib-agent:fpga-programming--verification-expert·LibraryAgentverification-expert
- lib-agent:fpga-programming--synthesis-expert·LibraryAgentsynthesis-expert
Incoming edges
None.