II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--vhdl-module-development
specializations/fpga-programming/vhdl-module-development overview
VHDL Module Development - Develop synthesizable VHDL modules following IEEE 1076 standards and industry best practices. Implement entities, architectures, and packages with proper use of numeric_std library and synchronous design methodology.
Attributes
displayName
specializations/fpga-programming/vhdl-module-development
description
VHDL Module Development - Develop synthesizable VHDL modules following IEEE 1076 standards and industry
best practices. Implement entities, architectures, and packages with proper use of numeric_std library and synchronous
design methodology.
libraryPath
library/specializations/fpga-programming/vhdl-module-development.js
specialization
fpga-programming
references
- - IEEE 1076-2019 VHDL Standard: https://standards.ieee.org/standard/1076-2019.html
- - VHDL RTL Synthesis: https://standards.ieee.org/standard/1076_6-2004.html
- - Xilinx VHDL Coding Guidelines: https://docs.amd.com/r/en-US/ug901-vivado-synthesis
example
const result = await orchestrate('specializations/fpga-programming/vhdl-module-development', {
moduleName: 'fifo_sync',
functionality: 'Synchronous FIFO with configurable depth and width',
targetDevice: 'Xilinx Artix-7',
interfaces: ['data_in[WIDTH-1:0]', 'data_out[WIDTH-1:0]', 'wr_en', 'rd_en'],
generics: ['WIDTH: positive := 8', 'DEPTH: positive := 16']
});
usesAgents
- rtl-design-expert
- synthesis-expert
- verification-expert
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:hardware-software-integration·WorkflowHardware-Software Integration
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
uses_agent3
- lib-agent:fpga-programming--rtl-design-expert·LibraryAgentrtl-design-expert
- lib-agent:fpga-programming--synthesis-expert·LibraryAgentsynthesis-expert
- lib-agent:fpga-programming--verification-expert·LibraryAgentverification-expert
Incoming edges
None.