II.
LibraryAgent JSON
Structured · livelib-agent:fpga-programming--rtl-design-expert
rtl-design-expert json
Inspect the normalized record payload exactly as the atlas UI reads it.
{
"id": "lib-agent:fpga-programming--rtl-design-expert",
"_kind": "LibraryAgent",
"_file": "generated-library/agents.yaml",
"_cluster": "generated-library",
"attributes": {
"displayName": "rtl-design-expert",
"description": "Senior RTL designer with deep expertise in synthesizable HDL code for FPGA designs",
"libraryPath": "library/specializations/fpga-programming/agents/rtl-design-expert/AGENT.md",
"specialization": "fpga-programming",
"role": "Senior RTL Design Engineer",
"expertise": [
"VHDL best practices and IEEE 1076 compliance",
"Verilog/SystemVerilog best practices and IEEE 1800 compliance",
"Synchronous design methodology",
"Pipeline design and optimization",
"Resource sharing and area optimization",
"Clock and reset design patterns",
"Parameterizable and reusable RTL",
"Synthesis-friendly coding styles"
]
},
"outgoingEdges": [
{
"from": "lib-agent:fpga-programming--rtl-design-expert",
"to": "skill-area:hdl-design",
"kind": "lib_requires_skill_area",
"attributes": {
"weight": 1
}
},
{
"from": "lib-agent:fpga-programming--rtl-design-expert",
"to": "skill-area:fpga-synthesis",
"kind": "lib_requires_skill_area",
"attributes": {
"weight": 0.7
}
},
{
"from": "lib-agent:fpga-programming--rtl-design-expert",
"to": "domain:embedded-systems",
"kind": "lib_applies_to_domain",
"attributes": {
"weight": 1
}
},
{
"from": "lib-agent:fpga-programming--rtl-design-expert",
"to": "role:embedded-engineer",
"kind": "lib_involves_role",
"attributes": {
"weight": 1
}
},
{
"from": "lib-agent:fpga-programming--rtl-design-expert",
"to": "specialization:fpga-programming",
"kind": "lib_belongs_to_specialization",
"attributes": {
"weight": 1
}
}
],
"incomingEdges": [
{
"from": "lib-process:fpga-programming--fsm-design",
"to": "lib-agent:fpga-programming--rtl-design-expert",
"kind": "uses_agent",
"attributes": {
"weight": 0.8
}
},
{
"from": "lib-process:fpga-programming--pipeline-architecture",
"to": "lib-agent:fpga-programming--rtl-design-expert",
"kind": "uses_agent",
"attributes": {
"weight": 0.8
}
},
{
"from": "lib-process:fpga-programming--rtl-module-architecture",
"to": "lib-agent:fpga-programming--rtl-design-expert",
"kind": "uses_agent",
"attributes": {
"weight": 0.8
}
},
{
"from": "lib-process:fpga-programming--verilog-systemverilog-design",
"to": "lib-agent:fpga-programming--rtl-design-expert",
"kind": "uses_agent",
"attributes": {
"weight": 0.8
}
},
{
"from": "lib-process:fpga-programming--vhdl-module-development",
"to": "lib-agent:fpga-programming--rtl-design-expert",
"kind": "uses_agent",
"attributes": {
"weight": 0.8
}
}
]
}