II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--rtl-module-architecture
specializations/fpga-programming/rtl-module-architecture overview
RTL Module Architecture Design - Design and document the architecture for RTL modules including interface definitions, internal data paths, control logic, and timing requirements. Establish module hierarchy and define signal naming conventions.
Attributes
displayName
specializations/fpga-programming/rtl-module-architecture
description
RTL Module Architecture Design - Design and document the architecture for RTL modules including interface
definitions, internal data paths, control logic, and timing requirements. Establish module hierarchy and define signal
naming conventions.
libraryPath
library/specializations/fpga-programming/rtl-module-architecture.js
specialization
fpga-programming
references
- - RTL Design Best Practices: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html
- - FPGA Architecture Design: https://docs.amd.com/r/en-US/ug949-vivado-design-methodology
- - Hardware Design Patterns: https://zipcpu.com/
example
const result = await orchestrate('specializations/fpga-programming/rtl-module-architecture', {
moduleName: 'DataStreamProcessor',
targetDevice: 'Xilinx Artix-7',
interfaces: ['AXI4-Stream input', 'AXI4-Stream output', 'AXI4-Lite config'],
clockDomains: ['sys_clk@100MHz'],
functionality: 'Real-time data filtering and transformation pipeline'
});
usesAgents
- fpga-architect
- rtl-design-expert
- fpga-timing-expert
- technical-writer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:architecture-decision-record·WorkflowArchitecture Decision Record
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
uses_agent4
- lib-agent:fpga-programming--fpga-architect·LibraryAgentfpga-architect
- lib-agent:fpga-programming--rtl-design-expert·LibraryAgentrtl-design-expert
- lib-agent:fpga-programming--fpga-timing-expert·LibraryAgentfpga-timing-expert
- lib-agent:meta--technical-writer·LibraryAgenttechnical-writer
Incoming edges
None.