II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--fsm-design
specializations/fpga-programming/fsm-design overview
Finite State Machine (FSM) Design - Design and implement finite state machines using one-hot, binary, or Gray encoding. Create clear state transition logic with proper reset behavior and output registration.
Attributes
displayName
specializations/fpga-programming/fsm-design
description
Finite State Machine (FSM) Design - Design and implement finite state machines using one-hot, binary,
or Gray encoding. Create clear state transition logic with proper reset behavior and output registration.
libraryPath
library/specializations/fpga-programming/fsm-design.js
specialization
fpga-programming
references
- - FSM Design Best Practices: http://www.sunburst-design.com/papers/
- - State Machine Encoding: https://docs.amd.com/r/en-US/ug901-vivado-synthesis
- - Safe FSM Design: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html
example
const result = await orchestrate('specializations/fpga-programming/fsm-design', {
fsmName: 'uart_tx_fsm',
stateList: ['IDLE', 'START_BIT', 'DATA_BITS', 'STOP_BIT'],
encoding: 'one-hot',
outputType: 'Moore',
targetDevice: 'Xilinx Artix-7',
language: 'SystemVerilog'
});
usesAgents
- rtl-design-expert
- verification-expert
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:architecture-decision-record·WorkflowArchitecture Decision Record
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
uses_agent2
- lib-agent:fpga-programming--rtl-design-expert·LibraryAgentrtl-design-expert
- lib-agent:fpga-programming--verification-expert·LibraryAgentverification-expert
Incoming edges
None.