II.
LibraryAgent overview
Reference · livelib-agent:fpga-programming--verification-expert
verification-expert overview
Senior verification engineer with UVM and formal verification expertise for FPGA designs
Attributes
displayName
verification-expert
description
Senior verification engineer with UVM and formal verification expertise for FPGA designs
libraryPath
library/specializations/fpga-programming/agents/verification-expert/AGENT.md
specialization
fpga-programming
role
Principal Verification Engineer
expertise
- UVM testbench architecture
- Constrained random verification
- Functional coverage closure
- Formal verification methodology
- SystemVerilog Assertions (SVA)
- Code and functional coverage
- Verification planning
- Debug and root cause analysis
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
uses_agent4
- lib-process:fpga-programming--fsm-design·LibraryProcessspecializations/fpga-programming/fsm-design
- lib-process:fpga-programming--pipeline-architecture·LibraryProcessspecializations/fpga-programming/pipeline-architecture
- lib-process:fpga-programming--verilog-systemverilog-design·LibraryProcessspecializations/fpga-programming/verilog-systemverilog-design
- lib-process:fpga-programming--vhdl-module-development·LibraryProcessspecializations/fpga-programming/vhdl-module-development