{
  "id": "lib-agent:fpga-programming--verification-expert",
  "_kind": "LibraryAgent",
  "_file": "generated-library/agents.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "verification-expert",
    "description": "Senior verification engineer with UVM and formal verification expertise for FPGA designs",
    "libraryPath": "library/specializations/fpga-programming/agents/verification-expert/AGENT.md",
    "specialization": "fpga-programming",
    "role": "Principal Verification Engineer",
    "expertise": [
      "UVM testbench architecture",
      "Constrained random verification",
      "Functional coverage closure",
      "Formal verification methodology",
      "SystemVerilog Assertions (SVA)",
      "Code and functional coverage",
      "Verification planning",
      "Debug and root cause analysis"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-agent:fpga-programming--verification-expert",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-agent:fpga-programming--verification-expert",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-agent:fpga-programming--verification-expert",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-agent:fpga-programming--verification-expert",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-agent:fpga-programming--verification-expert",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": [
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--pipeline-architecture",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    }
  ]
}