{
  "id": "lib-process:fpga-programming--vhdl-module-development",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/vhdl-module-development",
    "description": "VHDL Module Development - Develop synthesizable VHDL modules following IEEE 1076 standards and industry\nbest practices. Implement entities, architectures, and packages with proper use of numeric_std library and synchronous\ndesign methodology.",
    "libraryPath": "library/specializations/fpga-programming/vhdl-module-development.js",
    "specialization": "fpga-programming",
    "references": [
      "- IEEE 1076-2019 VHDL Standard: https://standards.ieee.org/standard/1076-2019.html",
      "- VHDL RTL Synthesis: https://standards.ieee.org/standard/1076_6-2004.html",
      "- Xilinx VHDL Coding Guidelines: https://docs.amd.com/r/en-US/ug901-vivado-synthesis"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/vhdl-module-development', {\n  moduleName: 'fifo_sync',\n  functionality: 'Synchronous FIFO with configurable depth and width',\n  targetDevice: 'Xilinx Artix-7',\n  interfaces: ['data_in[WIDTH-1:0]', 'data_out[WIDTH-1:0]', 'wr_en', 'rd_en'],\n  generics: ['WIDTH: positive := 8', 'DEPTH: positive := 16']\n});",
    "usesAgents": [
      "rtl-design-expert",
      "synthesis-expert",
      "verification-expert"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "workflow:hardware-software-integration",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "lib-agent:fpga-programming--rtl-design-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "lib-agent:fpga-programming--synthesis-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--vhdl-module-development",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    }
  ],
  "incomingEdges": []
}