{
  "id": "lib-process:fpga-programming--verilog-systemverilog-design",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/verilog-systemverilog-design",
    "description": "Verilog/SystemVerilog Design Implementation - Implement digital designs using Verilog or SystemVerilog\nfollowing IEEE 1800 standards. Create parameterized modules with proper use of always_ff, always_comb, and interface\nconstructs.",
    "libraryPath": "library/specializations/fpga-programming/verilog-systemverilog-design.js",
    "specialization": "fpga-programming",
    "references": [
      "- IEEE 1800-2023 SystemVerilog: https://standards.ieee.org/standard/1800-2023.html",
      "- Verilog IEEE 1364-2005: https://standards.ieee.org/standard/1364-2005.html",
      "- SystemVerilog for Design: https://www.veripool.org/verilator/"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/verilog-systemverilog-design', {\n  moduleName: 'axi_stream_filter',\n  functionality: 'AXI-Stream data filter with configurable threshold',\n  language: 'SystemVerilog',\n  targetDevice: 'Intel Agilex',\n  interfaces: ['axi_stream_if.slave s_axis', 'axi_stream_if.master m_axis'],\n  parameters: ['DATA_WIDTH = 32', 'THRESHOLD = 128']\n});",
    "usesAgents": [
      "rtl-design-expert",
      "verification-expert",
      "synthesis-expert"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "lib-agent:fpga-programming--rtl-design-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--verilog-systemverilog-design",
      "to": "lib-agent:fpga-programming--synthesis-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    }
  ],
  "incomingEdges": []
}