{
  "id": "lib-process:fpga-programming--fsm-design",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/fsm-design",
    "description": "Finite State Machine (FSM) Design - Design and implement finite state machines using one-hot, binary,\nor Gray encoding. Create clear state transition logic with proper reset behavior and output registration.",
    "libraryPath": "library/specializations/fpga-programming/fsm-design.js",
    "specialization": "fpga-programming",
    "references": [
      "- FSM Design Best Practices: http://www.sunburst-design.com/papers/",
      "- State Machine Encoding: https://docs.amd.com/r/en-US/ug901-vivado-synthesis",
      "- Safe FSM Design: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/fsm-design', {\n  fsmName: 'uart_tx_fsm',\n  stateList: ['IDLE', 'START_BIT', 'DATA_BITS', 'STOP_BIT'],\n  encoding: 'one-hot',\n  outputType: 'Moore',\n  targetDevice: 'Xilinx Artix-7',\n  language: 'SystemVerilog'\n});",
    "usesAgents": [
      "rtl-design-expert",
      "verification-expert"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "lib-agent:fpga-programming--rtl-design-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--fsm-design",
      "to": "lib-agent:fpga-programming--verification-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    }
  ],
  "incomingEdges": []
}