{
  "id": "lib-process:fpga-programming--rtl-module-architecture",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/rtl-module-architecture",
    "description": "RTL Module Architecture Design - Design and document the architecture for RTL modules including interface\ndefinitions, internal data paths, control logic, and timing requirements. Establish module hierarchy and define signal\nnaming conventions.",
    "libraryPath": "library/specializations/fpga-programming/rtl-module-architecture.js",
    "specialization": "fpga-programming",
    "references": [
      "- RTL Design Best Practices: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html",
      "- FPGA Architecture Design: https://docs.amd.com/r/en-US/ug949-vivado-design-methodology",
      "- Hardware Design Patterns: https://zipcpu.com/"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/rtl-module-architecture', {\n  moduleName: 'DataStreamProcessor',\n  targetDevice: 'Xilinx Artix-7',\n  interfaces: ['AXI4-Stream input', 'AXI4-Stream output', 'AXI4-Lite config'],\n  clockDomains: ['sys_clk@100MHz'],\n  functionality: 'Real-time data filtering and transformation pipeline'\n});",
    "usesAgents": [
      "fpga-architect",
      "rtl-design-expert",
      "fpga-timing-expert",
      "technical-writer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "lib-agent:fpga-programming--fpga-architect",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "lib-agent:fpga-programming--rtl-design-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "lib-agent:fpga-programming--fpga-timing-expert",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    },
    {
      "from": "lib-process:fpga-programming--rtl-module-architecture",
      "to": "lib-agent:meta--technical-writer",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    }
  ],
  "incomingEdges": []
}