{
  "id": "role:fpga-engineer",
  "_kind": "Role",
  "_file": "role/roles/roles-expanded-2.yaml",
  "_cluster": "role",
  "attributes": {
    "displayName": "FPGA Engineer",
    "isAgentic": false,
    "requiredCapabilities": [],
    "requiredDomains": [],
    "description": "Designs and implements digital logic on field-programmable gate arrays —\nHDL coding, synthesis, place-and-route, timing closure, and hardware\nverification using UVM or cocotb.\n"
  },
  "outgoingEdges": [
    {
      "from": "role:fpga-engineer",
      "to": "responsibility:performance-optimization",
      "kind": "holds_responsibility"
    },
    {
      "from": "role:fpga-engineer",
      "to": "responsibility:test-strategy",
      "kind": "holds_responsibility"
    },
    {
      "from": "role:fpga-engineer",
      "to": "skill-area:hdl-design",
      "kind": "requires_expertise",
      "attributes": {}
    },
    {
      "from": "role:fpga-engineer",
      "to": "skill-area:fpga-synthesis",
      "kind": "requires_expertise",
      "attributes": {}
    },
    {
      "from": "role:fpga-engineer",
      "to": "skill-area:timing-closure",
      "kind": "requires_expertise",
      "attributes": {}
    },
    {
      "from": "role:fpga-engineer",
      "to": "skill-area:hardware-verification-uvm",
      "kind": "requires_expertise",
      "attributes": {}
    },
    {
      "from": "role:fpga-engineer",
      "to": "domain:embedded-systems",
      "kind": "applies_to",
      "attributes": {}
    },
    {
      "from": "role:fpga-engineer",
      "to": "domain:semiconductor-design",
      "kind": "applies_to",
      "attributes": {}
    }
  ],
  "incomingEdges": []
}