{
  "id": "lib-skill:fpga-programming--timing-constraints",
  "_kind": "LibrarySkill",
  "_file": "generated-library/skills.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "timing-constraints",
    "description": "Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.",
    "libraryPath": "library/specializations/fpga-programming/skills/timing-constraints/SKILL.md",
    "specialization": "fpga-programming",
    "contentSummary": "# Timing Constraints Skill\n\nExpert skill for FPGA timing constraint development following SDC (Synopsys Design Constraints) and Xilinx XDC standards. Provides deep expertise in clock definition, I/O timing, false paths, multicycle paths, and constraint validation.\n\n## Overview\n\nThe Timing Constraint"
  },
  "outgoingEdges": [
    {
      "from": "lib-skill:fpga-programming--timing-constraints",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-skill:fpga-programming--timing-constraints",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-skill:fpga-programming--timing-constraints",
      "to": "skill-area:timing-closure",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.5
      }
    },
    {
      "from": "lib-skill:fpga-programming--timing-constraints",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-skill:fpga-programming--timing-constraints",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-skill:fpga-programming--timing-constraints",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}