II.
LibrarySkill overview
Reference · livelib-skill:fpga-programming--timing-constraints
timing-constraints overview
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
Attributes
displayName
timing-constraints
description
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
libraryPath
library/specializations/fpga-programming/skills/timing-constraints/SKILL.md
specialization
fpga-programming
contentSummary
# Timing Constraints Skill
Expert skill for FPGA timing constraint development following SDC (Synopsys Design Constraints) and Xilinx XDC standards. Provides deep expertise in clock definition, I/O timing, false paths, multicycle paths, and constraint validation.
## Overview
The Timing Constraint
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area3
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
- skill-area:timing-closure·SkillAreaTiming Closure
Incoming edges
None.