{
  "id": "lib-skill:fpga-programming--formal-verification",
  "_kind": "LibrarySkill",
  "_file": "generated-library/skills.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "formal-verification",
    "description": "Formal property verification and model checking skill for FPGA designs",
    "libraryPath": "library/specializations/fpga-programming/skills/formal-verification/SKILL.md",
    "specialization": "fpga-programming",
    "contentSummary": "# Formal Verification Skill\n\n## Overview\n\nExpert skill for formal property verification and model checking, enabling exhaustive verification of FPGA design properties without simulation.\n\n## Capabilities\n\n- Write properties for formal verification\n- Configure formal tool constraints\n- Analyze formal"
  },
  "outgoingEdges": [
    {
      "from": "lib-skill:fpga-programming--formal-verification",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-skill:fpga-programming--formal-verification",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-skill:fpga-programming--formal-verification",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-skill:fpga-programming--formal-verification",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-skill:fpga-programming--formal-verification",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}