{
  "id": "lib-skill:fpga-programming--cdc-analysis",
  "_kind": "LibrarySkill",
  "_file": "generated-library/skills.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "cdc-analysis",
    "description": "Specialized skill for clock domain crossing analysis and synchronizer design in FPGA designs",
    "libraryPath": "library/specializations/fpga-programming/skills/cdc-analysis/SKILL.md",
    "specialization": "fpga-programming",
    "contentSummary": "# CDC Analysis Skill\n\n## Overview\n\nExpert skill for Clock Domain Crossing (CDC) analysis and synchronizer design, ensuring metastability-safe multi-clock FPGA designs.\n\n## Capabilities\n\n- Identify all clock domain crossings in RTL\n- Design 2FF and 3FF synchronizers with ASYNC_REG\n- Implement Gray co"
  },
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}