II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--uvm-testbench
specializations/fpga-programming/uvm-testbench overview
UVM Testbench Architecture - Design and implement Universal Verification Methodology (UVM) testbenches following IEEE 1800.2 standard. Create reusable verification components and test infrastructure.
Attributes
displayName
specializations/fpga-programming/uvm-testbench
description
UVM Testbench Architecture - Design and implement Universal Verification Methodology (UVM) testbenches
following IEEE 1800.2 standard. Create reusable verification components and test infrastructure.
libraryPath
library/specializations/fpga-programming/uvm-testbench.js
specialization
fpga-programming
references
- - IEEE 1800.2-2020 UVM Standard: https://standards.ieee.org/standard/1800_2-2020.html
- - UVM Reference: https://verificationacademy.com/
- - UVM Cookbook: https://www.mentor.com/
example
const result = await orchestrate('specializations/fpga-programming/uvm-testbench', {
dutName: 'ethernet_mac',
interfaces: ['gmii', 'axi_lite', 'interrupt'],
uvmVersion: '1.2',
reuseLevel: 'high'
});
usesAgents
- uvm-architect
- uvm-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:hardware-software-integration·WorkflowHardware-Software Integration
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.