{
  "id": "lib-process:fpga-programming--timing-constraints",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/timing-constraints",
    "description": "Timing Constraint Development - Develop comprehensive timing constraints (SDC/XDC) including clock\ndefinitions, input/output delays, false paths, and multicycle paths. Ensure constraint completeness and correctness.",
    "libraryPath": "library/specializations/fpga-programming/timing-constraints.js",
    "specialization": "fpga-programming",
    "references": [
      "- SDC Standard: https://www.synopsys.com/",
      "- Vivado Constraints: https://docs.amd.com/r/en-US/ug903-vivado-using-constraints",
      "- Timing Analysis: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1410385117325.html"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/timing-constraints', {\n  designName: 'multi_clock_design',\n  clockSpecs: [{ name: 'sys_clk', frequency: 200, source: 'external' }, { name: 'ddr_clk', frequency: 400, source: 'pll' }],\n  ioInterfaces: ['ddr3', 'spi', 'uart'],\n  constraintFormat: 'XDC'\n});",
    "usesAgents": [
      "timing-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "skill-area:timing-closure",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.5
      }
    },
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "workflow:ml-model-lifecycle",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--timing-constraints",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}