II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--timing-constraints
specializations/fpga-programming/timing-constraints overview
Timing Constraint Development - Develop comprehensive timing constraints (SDC/XDC) including clock definitions, input/output delays, false paths, and multicycle paths. Ensure constraint completeness and correctness.
Attributes
displayName
specializations/fpga-programming/timing-constraints
description
Timing Constraint Development - Develop comprehensive timing constraints (SDC/XDC) including clock
definitions, input/output delays, false paths, and multicycle paths. Ensure constraint completeness and correctness.
libraryPath
library/specializations/fpga-programming/timing-constraints.js
specialization
fpga-programming
references
- - SDC Standard: https://www.synopsys.com/
- - Vivado Constraints: https://docs.amd.com/r/en-US/ug903-vivado-using-constraints
- - Timing Analysis: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1410385117325.html
example
const result = await orchestrate('specializations/fpga-programming/timing-constraints', {
designName: 'multi_clock_design',
clockSpecs: [{ name: 'sys_clk', frequency: 200, source: 'external' }, { name: 'ddr_clk', frequency: 400, source: 'pll' }],
ioInterfaces: ['ddr3', 'spi', 'uart'],
constraintFormat: 'XDC'
});
usesAgents
- timing-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:ml-model-lifecycle·WorkflowML Model Lifecycle
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area3
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
- skill-area:timing-closure·SkillAreaTiming Closure
Incoming edges
None.