{
  "id": "lib-process:fpga-programming--testbench-development",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/testbench-development",
    "description": "Testbench Development - Create comprehensive testbenches for RTL verification including stimulus\ngeneration, response checking, and coverage collection. Use SystemVerilog verification features or VHDL testbench\npatterns.",
    "libraryPath": "library/specializations/fpga-programming/testbench-development.js",
    "specialization": "fpga-programming",
    "references": [
      "- SystemVerilog for Verification: https://verificationacademy.com/",
      "- Writing Testbenches: https://www.veripool.org/verilator/",
      "- VHDL Verification: https://vunit.github.io/"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/testbench-development', {\n  dutName: 'axi_dma_controller',\n  dutInterfaces: ['axi4_lite_if', 'axi4_mm_if', 'interrupt'],\n  language: 'SystemVerilog',\n  verificationLevel: 'comprehensive',\n  coverageGoals: { functional: 90, code: 85 }\n});",
    "usesAgents": [
      "verification-engineer",
      "verification-architect"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--testbench-development",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--testbench-development",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--testbench-development",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--testbench-development",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--testbench-development",
      "to": "workflow:hardware-software-integration",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--testbench-development",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}