II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--testbench-development
specializations/fpga-programming/testbench-development overview
Testbench Development - Create comprehensive testbenches for RTL verification including stimulus generation, response checking, and coverage collection. Use SystemVerilog verification features or VHDL testbench patterns.
Attributes
displayName
specializations/fpga-programming/testbench-development
description
Testbench Development - Create comprehensive testbenches for RTL verification including stimulus
generation, response checking, and coverage collection. Use SystemVerilog verification features or VHDL testbench
patterns.
libraryPath
library/specializations/fpga-programming/testbench-development.js
specialization
fpga-programming
references
- - SystemVerilog for Verification: https://verificationacademy.com/
- - Writing Testbenches: https://www.veripool.org/verilator/
- - VHDL Verification: https://vunit.github.io/
example
const result = await orchestrate('specializations/fpga-programming/testbench-development', {
dutName: 'axi_dma_controller',
dutInterfaces: ['axi4_lite_if', 'axi4_mm_if', 'interrupt'],
language: 'SystemVerilog',
verificationLevel: 'comprehensive',
coverageGoals: { functional: 90, code: 85 }
});
usesAgents
- verification-engineer
- verification-architect
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:hardware-software-integration·WorkflowHardware-Software Integration
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.