{
  "id": "lib-process:fpga-programming--synthesis-optimization",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/synthesis-optimization",
    "description": "Synthesis Optimization - Optimize RTL for synthesis to meet area, timing, and power goals. Apply\nsynthesis directives and attributes to guide tool optimization.",
    "libraryPath": "library/specializations/fpga-programming/synthesis-optimization.js",
    "specialization": "fpga-programming",
    "references": [
      "- Vivado Synthesis: https://docs.amd.com/r/en-US/ug901-vivado-synthesis",
      "- Quartus Synthesis: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html",
      "- Synthesis Best Practices: https://docs.amd.com/r/en-US/ug949-vivado-design-methodology"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/synthesis-optimization', {\n  designName: 'video_processor',\n  targetDevice: 'Xilinx Ultrascale+ XCVU9P',\n  optimizationGoals: { targetFrequency: 300, maxLutUtilization: 70, powerBudget: 15 },\n  synthesisToolset: 'Vivado'\n});",
    "usesAgents": [
      "synthesis-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "skill-area:timing-closure",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.5
      }
    },
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "workflow:hardware-software-integration",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--synthesis-optimization",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}