II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--synthesis-optimization
specializations/fpga-programming/synthesis-optimization overview
Synthesis Optimization - Optimize RTL for synthesis to meet area, timing, and power goals. Apply synthesis directives and attributes to guide tool optimization.
Attributes
displayName
specializations/fpga-programming/synthesis-optimization
description
Synthesis Optimization - Optimize RTL for synthesis to meet area, timing, and power goals. Apply
synthesis directives and attributes to guide tool optimization.
libraryPath
library/specializations/fpga-programming/synthesis-optimization.js
specialization
fpga-programming
references
- - Vivado Synthesis: https://docs.amd.com/r/en-US/ug901-vivado-synthesis
- - Quartus Synthesis: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html
- - Synthesis Best Practices: https://docs.amd.com/r/en-US/ug949-vivado-design-methodology
example
const result = await orchestrate('specializations/fpga-programming/synthesis-optimization', {
designName: 'video_processor',
targetDevice: 'Xilinx Ultrascale+ XCVU9P',
optimizationGoals: { targetFrequency: 300, maxLutUtilization: 70, powerBudget: 15 },
synthesisToolset: 'Vivado'
});
usesAgents
- synthesis-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:hardware-software-integration·WorkflowHardware-Software Integration
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area3
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
- skill-area:timing-closure·SkillAreaTiming Closure
Incoming edges
None.