II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--sva-development
specializations/fpga-programming/sva-development overview
SystemVerilog Assertion (SVA) Development - Implement concurrent and immediate assertions to verify design properties. Create assertion libraries for protocol checking and design intent specification.
Attributes
displayName
specializations/fpga-programming/sva-development
description
SystemVerilog Assertion (SVA) Development - Implement concurrent and immediate assertions to verify
design properties. Create assertion libraries for protocol checking and design intent specification.
libraryPath
library/specializations/fpga-programming/sva-development.js
specialization
fpga-programming
references
- - SystemVerilog Assertions: https://www.accellera.org/
- - SVA Handbook: https://verificationacademy.com/
- - Formal Verification with SVA: https://www.synopsys.com/verification/static-and-formal-verification.html
example
const result = await orchestrate('specializations/fpga-programming/sva-development', {
designName: 'axi_master',
protocols: ['AXI4', 'AXI4-Lite'],
designIntentProperties: ['no_deadlock', 'data_integrity', 'handshake_timeout'],
assertionLevel: 'comprehensive'
});
usesAgents
- verification-engineer
- sva-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:hardware-software-integration·WorkflowHardware-Software Integration
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.