iiRecord
Agentic AI Atlas · specializations/fpga-programming/reset-strategy
lib-process:fpga-programming--reset-strategya5c.ai
II.
LibraryProcess JSON

lib-process:fpga-programming--reset-strategy

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specializations/fpga-programming/reset-strategy json

Inspect the normalized record payload exactly as the atlas UI reads it.

File · generated-library/processes.yamlCluster · generated-library
Record JSON
{
  "id": "lib-process:fpga-programming--reset-strategy",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/reset-strategy",
    "description": "Reset Strategy Design - Design robust reset distribution and synchronization for single and multi-clock\ndomain designs. Implement reset sequencing and de-assertion synchronization.",
    "libraryPath": "library/specializations/fpga-programming/reset-strategy.js",
    "specialization": "fpga-programming",
    "references": [
      "- Reset Design: http://www.sunburst-design.com/papers/",
      "- FPGA Reset Best Practices: https://docs.amd.com/r/en-US/ug949-vivado-design-methodology"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/reset-strategy', {\n  designName: 'soc_subsystem',\n  clockDomains: ['cpu_clk', 'bus_clk', 'io_clk'],\n  resetType: 'synchronous',\n  resetPolarity: 'active_low'\n});",
    "usesAgents": [
      "fpga-engineer",
      "timing-engineer",
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--reset-strategy",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--reset-strategy",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--reset-strategy",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--reset-strategy",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--reset-strategy",
      "to": "workflow:strategic-planning",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--reset-strategy",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}