II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--reset-strategy
specializations/fpga-programming/reset-strategy overview
Reset Strategy Design - Design robust reset distribution and synchronization for single and multi-clock domain designs. Implement reset sequencing and de-assertion synchronization.
Attributes
displayName
specializations/fpga-programming/reset-strategy
description
Reset Strategy Design - Design robust reset distribution and synchronization for single and multi-clock
domain designs. Implement reset sequencing and de-assertion synchronization.
libraryPath
library/specializations/fpga-programming/reset-strategy.js
specialization
fpga-programming
references
- - Reset Design: http://www.sunburst-design.com/papers/
- - FPGA Reset Best Practices: https://docs.amd.com/r/en-US/ug949-vivado-design-methodology
example
const result = await orchestrate('specializations/fpga-programming/reset-strategy', {
designName: 'soc_subsystem',
clockDomains: ['cpu_clk', 'bus_clk', 'io_clk'],
resetType: 'synchronous',
resetPolarity: 'active_low'
});
usesAgents
- fpga-engineer
- timing-engineer
- verification-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:strategic-planning·WorkflowStrategic Planning
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.