II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--design-for-testability
specializations/fpga-programming/design-for-testability overview
Design for Testability (DFT) - Implement JTAG boundary scan, BIST (Built-In Self Test), and production test infrastructure. Enable efficient manufacturing test and field diagnostics.
Attributes
displayName
specializations/fpga-programming/design-for-testability
description
Design for Testability (DFT) - Implement JTAG boundary scan, BIST (Built-In Self Test), and production
test infrastructure. Enable efficient manufacturing test and field diagnostics.
libraryPath
library/specializations/fpga-programming/design-for-testability.js
specialization
fpga-programming
references
- - IEEE 1149.1 JTAG: https://standards.ieee.org/standard/1149_1-2013.html
- - IEEE 1500 Embedded Core Test: https://standards.ieee.org/standard/1500-2005.html
- - FPGA BIST Techniques: https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging
example
const result = await orchestrate('specializations/fpga-programming/design-for-testability', {
designName: 'network_processor',
testStrategy: 'comprehensive',
jtagSupport: true,
bistModules: ['memory_bist', 'logic_bist']
});
usesAgents
- dft-engineer
- verification-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:architecture-decision-record·WorkflowArchitecture Decision Record
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.