{
  "id": "lib-process:fpga-programming--constrained-random-verification",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/constrained-random-verification",
    "description": "Constrained Random Verification (CRV) - Develop constrained random testbenches using SystemVerilog\nrandomization features. Create constraint classes and coverage models for thorough verification.",
    "libraryPath": "library/specializations/fpga-programming/constrained-random-verification.js",
    "specialization": "fpga-programming",
    "references": [
      "- SystemVerilog for Verification: https://verificationacademy.com/",
      "- Constrained Random Verification: https://www.mentor.com/",
      "- Coverage-Driven Verification: https://www.cadence.com/"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/constrained-random-verification', {\n  dutName: 'dma_engine',\n  interfaces: ['axi4_mm', 'axi4_stream', 'interrupt'],\n  coverageGoals: { functional: 95, code: 90 },\n  constraintComplexity: 'high'\n});",
    "usesAgents": [
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--constrained-random-verification",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--constrained-random-verification",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--constrained-random-verification",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--constrained-random-verification",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--constrained-random-verification",
      "to": "workflow:hardware-software-integration",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--constrained-random-verification",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}