II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--constrained-random-verification
specializations/fpga-programming/constrained-random-verification overview
Constrained Random Verification (CRV) - Develop constrained random testbenches using SystemVerilog randomization features. Create constraint classes and coverage models for thorough verification.
Attributes
displayName
specializations/fpga-programming/constrained-random-verification
description
Constrained Random Verification (CRV) - Develop constrained random testbenches using SystemVerilog
randomization features. Create constraint classes and coverage models for thorough verification.
libraryPath
library/specializations/fpga-programming/constrained-random-verification.js
specialization
fpga-programming
references
- - SystemVerilog for Verification: https://verificationacademy.com/
- - Constrained Random Verification: https://www.mentor.com/
- - Coverage-Driven Verification: https://www.cadence.com/
example
const result = await orchestrate('specializations/fpga-programming/constrained-random-verification', {
dutName: 'dma_engine',
interfaces: ['axi4_mm', 'axi4_stream', 'interrupt'],
coverageGoals: { functional: 95, code: 90 },
constraintComplexity: 'high'
});
usesAgents
- verification-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:hardware-software-integration·WorkflowHardware-Software Integration
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.