{
  "id": "lib-process:fpga-programming--clock-network-design",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/clock-network-design",
    "description": "Clock Network Design and Constraints - Design clock distribution networks using global and regional\nclock resources. Define clock relationships and constraints for derived clocks and PLLs/MMCMs.",
    "libraryPath": "library/specializations/fpga-programming/clock-network-design.js",
    "specialization": "fpga-programming",
    "references": [
      "- Xilinx Clocking Resources: https://docs.amd.com/r/en-US/ug472_7Series_Clocking",
      "- Intel Clock Networks: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/clock-network-design', {\n  designName: 'video_interface',\n  clockRequirements: [{ name: 'pixel_clk', frequency: 148.5 }, { name: 'ddr_clk', frequency: 400 }],\n  targetDevice: 'Xilinx Artix-7 XC7A100T',\n  pllConfiguration: { type: 'MMCM', inputFrequency: 100 }\n});",
    "usesAgents": [
      "clock-engineer",
      "timing-engineer",
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--clock-network-design",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--clock-network-design",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--clock-network-design",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--clock-network-design",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--clock-network-design",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--clock-network-design",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}