II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--clock-network-design
specializations/fpga-programming/clock-network-design overview
Clock Network Design and Constraints - Design clock distribution networks using global and regional clock resources. Define clock relationships and constraints for derived clocks and PLLs/MMCMs.
Attributes
displayName
specializations/fpga-programming/clock-network-design
description
Clock Network Design and Constraints - Design clock distribution networks using global and regional
clock resources. Define clock relationships and constraints for derived clocks and PLLs/MMCMs.
libraryPath
library/specializations/fpga-programming/clock-network-design.js
specialization
fpga-programming
references
- - Xilinx Clocking Resources: https://docs.amd.com/r/en-US/ug472_7Series_Clocking
- - Intel Clock Networks: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960181641.html
example
const result = await orchestrate('specializations/fpga-programming/clock-network-design', {
designName: 'video_interface',
clockRequirements: [{ name: 'pixel_clk', frequency: 148.5 }, { name: 'ddr_clk', frequency: 400 }],
targetDevice: 'Xilinx Artix-7 XC7A100T',
pllConfiguration: { type: 'MMCM', inputFrequency: 100 }
});
usesAgents
- clock-engineer
- timing-engineer
- verification-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:architecture-decision-record·WorkflowArchitecture Decision Record
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.