{
  "id": "lib-process:fpga-programming--cdc-design",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/cdc-design",
    "description": "Clock Domain Crossing (CDC) Design - Design and verify safe clock domain crossing circuits. Implement\nsynchronizers, handshake protocols, and asynchronous FIFOs with proper CDC techniques.",
    "libraryPath": "library/specializations/fpga-programming/cdc-design.js",
    "specialization": "fpga-programming",
    "references": [
      "- CDC Design Guidelines: http://www.sunburst-design.com/papers/",
      "- CDC Verification: https://www.synopsys.com/verification/static-and-formal-verification/spyglass.html",
      "- Async FIFO Design: https://zipcpu.com/blog/2017/10/20/cdc.html"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/cdc-design', {\n  designName: 'multi_clock_controller',\n  clockDomains: [{ name: 'clk_100', frequency: 100 }, { name: 'clk_200', frequency: 200 }],\n  crossingTypes: ['single_bit', 'bus', 'handshake', 'async_fifo'],\n  verificationLevel: 'comprehensive'\n});",
    "usesAgents": [
      "cdc-engineer",
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--cdc-design",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--cdc-design",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--cdc-design",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--cdc-design",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--cdc-design",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--cdc-design",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}