II.
LibraryProcess overview
Reference · livelib-process:fpga-programming--cdc-design
specializations/fpga-programming/cdc-design overview
Clock Domain Crossing (CDC) Design - Design and verify safe clock domain crossing circuits. Implement synchronizers, handshake protocols, and asynchronous FIFOs with proper CDC techniques.
Attributes
displayName
specializations/fpga-programming/cdc-design
description
Clock Domain Crossing (CDC) Design - Design and verify safe clock domain crossing circuits. Implement
synchronizers, handshake protocols, and asynchronous FIFOs with proper CDC techniques.
libraryPath
library/specializations/fpga-programming/cdc-design.js
specialization
fpga-programming
references
- - CDC Design Guidelines: http://www.sunburst-design.com/papers/
- - CDC Verification: https://www.synopsys.com/verification/static-and-formal-verification/spyglass.html
- - Async FIFO Design: https://zipcpu.com/blog/2017/10/20/cdc.html
example
const result = await orchestrate('specializations/fpga-programming/cdc-design', {
designName: 'multi_clock_controller',
clockDomains: [{ name: 'clk_100', frequency: 100 }, { name: 'clk_200', frequency: 200 }],
crossingTypes: ['single_bit', 'bus', 'handshake', 'async_fifo'],
verificationLevel: 'comprehensive'
});
usesAgents
- cdc-engineer
- verification-engineer
Outgoing edges
lib_applies_to_domain1
- domain:embedded-systems·DomainEmbedded Systems
lib_belongs_to_specialization1
- specialization:fpga-programming·Specialization
lib_implements_workflow1
- workflow:architecture-decision-record·WorkflowArchitecture Decision Record
lib_involves_role1
- role:embedded-engineer·RoleEmbedded Engineer
lib_requires_skill_area2
- skill-area:hdl-design·SkillAreaHDL Design
- skill-area:fpga-synthesis·SkillAreaFPGA Synthesis Flow
Incoming edges
None.