displayName
Signal Integrity Analysis
workflowKind
governance
triggerType
event-driven
typicalCadence
per-revision
complexity
single-team
description
Analyzes signal integrity for high-speed digital interfaces --
running IBIS/SPICE simulations for eye diagram compliance, validating
transmission line impedance matching, checking crosstalk budgets on
adjacent traces, verifying DDR/PCIe/USB timing margins, and
confirming EMI compliance through pre-layout and post-layout
simulations. Excludes PCB routing decisions.