workflow:fpga-bitstream-deployment

{
  "id": "workflow:fpga-bitstream-deployment",
  "_kind": "Workflow",
  "_file": "workflows/workflows/workflows-fpga.yaml",
  "_cluster": "workflows",
  "attributes": {
    "displayName": "FPGA Bitstream Deployment",
    "workflowKind": "release",
    "triggerType": "on-demand",
    "typicalCadence": "per-release",
    "complexity": "single-team",
    "description": "Builds, verifies, and deploys FPGA bitstreams to target hardware —\nsynthesizing HDL, running place-and-route, performing timing closure\nanalysis, validating against simulation, and flashing production\nboards with rollback provisions. Excludes HDL design work.\n"
  },
  "outgoingEdges": [
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "role:implementer",
      "kind": "involves_role",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "role:tech-lead",
      "kind": "involves_role",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "skill-area:editor-fluency",
      "kind": "requires_skill_area",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "domain:embedded-systems",
      "kind": "applies_to_domain",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "responsibility:approve-deploys",
      "kind": "triggers_responsibility",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "responsibility:release-coordination",
      "kind": "triggers_responsibility",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "org-unit:engineering",
      "kind": "performed_by_org_unit",
      "attributes": {}
    },
    {
      "from": "workflow:fpga-bitstream-deployment",
      "to": "org-unit:research-engineering",
      "kind": "performed_by_org_unit",
      "attributes": {}
    }
  ],
  "incomingEdges": []
}