{
  "id": "stack-profile:fpga-development",
  "_kind": "StackProfile",
  "_file": "domain/stack-profiles/deep-stacks-5.yaml",
  "_cluster": "domain",
  "attributes": {
    "displayName": "FPGA Development (Python, Docker, Bash, Go, TypeScript)",
    "description": "An FPGA development and verification stack using hardware description\nlanguages for RTL design with Python-based testbenches for simulation\nand verification. Docker containers provide reproducible synthesis and\nsimulation environments across team members. Go tooling automates\nbitstream generation pipelines and register map code generation. Bash\nscripts orchestrate multi-step build flows from synthesis through\nplace-and-route to bitstream programming. Python's cocotb-style\nframeworks enable software engineers to write hardware testbenches in\nfamiliar languages. Targeted at hardware teams building custom\naccelerators, network processors, and signal processing pipelines. The\ntradeoff is extremely long synthesis times and the steep learning curve\nfor timing closure optimization.\n",
    "composes": [
      "language:python",
      "tool:docker",
      "language:bash",
      "language:go",
      "tool:github-actions",
      "library:pytest",
      "tool:make",
      "language:typescript"
    ]
  },
  "outgoingEdges": [
    {
      "from": "stack-profile:fpga-development",
      "to": "language:python",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "tool:docker",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "language:bash",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "language:go",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "tool:github-actions",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "library:pytest",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "tool:make",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "language:typescript",
      "kind": "composed_of"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "role:embedded-engineer",
      "kind": "used_by_role"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "role:research-engineer",
      "kind": "used_by_role"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "role:qa-engineer",
      "kind": "used_by_role"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "workflow:hardware-design-review",
      "kind": "follows_workflow"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "workflow:fpga-bitstream-deployment",
      "kind": "follows_workflow"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "domain:electrical-engineering",
      "kind": "applies_to"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "domain:embedded-systems",
      "kind": "applies_to"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "skill-area:hdl-design",
      "kind": "requires_skill_area"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "skill-area:fpga-synthesis",
      "kind": "requires_skill_area"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "skill-area:timing-closure",
      "kind": "requires_skill_area"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "skill-area:hardware-verification-uvm",
      "kind": "requires_skill_area"
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "skill-area:peripheral-interfacing",
      "kind": "requires_skill_area"
    }
  ],
  "incomingEdges": []
}