{
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  "_kind": "SkillArea",
  "_file": "domain/skill-areas/skill-areas-embedded-fpga.yaml",
  "_cluster": "domain",
  "attributes": {
    "displayName": "HDL Design",
    "description": "RTL design with Verilog/SystemVerilog/VHDL — clocking, reset,\nFSMs, pipelining, and synthesizable subsets.\n",
    "domains": [
      "specialization:fpga-programming"
    ],
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      "expert"
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}