{
  "id": "skill-area:hardware-verification-uvm",
  "_kind": "SkillArea",
  "_file": "domain/skill-areas/skill-areas-embedded-fpga.yaml",
  "_cluster": "domain",
  "attributes": {
    "displayName": "Hardware Verification (UVM)",
    "description": "SystemVerilog UVM verification environments — agents, sequences,\ncoverage models, and constrained random stimulus.\n",
    "domains": [
      "specialization:fpga-programming"
    ],
    "expertiseLevels": [
      "expert"
    ]
  },
  "outgoingEdges": [
    {
      "from": "skill-area:hardware-verification-uvm",
      "to": "specialization:fpga-programming",
      "kind": "applies_to",
      "attributes": {
        "confidence": "primary"
      }
    }
  ],
  "incomingEdges": [
    {
      "from": "skill-area:hdl-design",
      "to": "skill-area:hardware-verification-uvm",
      "kind": "prerequisite_for_learning",
      "attributes": {
        "strength": "recommended"
      }
    },
    {
      "from": "stack-profile:fpga-development",
      "to": "skill-area:hardware-verification-uvm",
      "kind": "requires_skill_area"
    },
    {
      "from": "lib-skill:fpga-programming--hardware-verification-uvm",
      "to": "skill-area:hardware-verification-uvm",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "role:fpga-engineer",
      "to": "skill-area:hardware-verification-uvm",
      "kind": "requires_expertise",
      "attributes": {}
    }
  ]
}