{
  "id": "lib-skill:fpga-programming--verilog-sv-language",
  "_kind": "LibrarySkill",
  "_file": "generated-library/skills.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "verilog-sv-language",
    "description": "Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.",
    "libraryPath": "library/specializations/fpga-programming/skills/verilog-sv-language/SKILL.md",
    "specialization": "fpga-programming",
    "contentSummary": "# Verilog/SystemVerilog Language Skill\n\nExpert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices.\n\n## Overview\n\nThe Verilog/SystemVerilog Langu"
  },
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        "weight": 1
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}