II.
LibrarySkill JSON
Structured · livelib-skill:fpga-programming--synthesis-optimization
synthesis-optimization json
Inspect the normalized record payload exactly as the atlas UI reads it.
{
"id": "lib-skill:fpga-programming--synthesis-optimization",
"_kind": "LibrarySkill",
"_file": "generated-library/skills.yaml",
"_cluster": "generated-library",
"attributes": {
"displayName": "synthesis-optimization",
"description": "Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.",
"libraryPath": "library/specializations/fpga-programming/skills/synthesis-optimization/SKILL.md",
"specialization": "fpga-programming",
"contentSummary": "# Synthesis Optimization Skill\n\nExpert skill for FPGA synthesis optimization targeting Vivado and Quartus tools. Provides deep expertise in synthesis report analysis, attribute application, resource inference control, and QoR (Quality of Results) improvement.\n\n## Overview\n\nThe Synthesis Optimization"
},
"outgoingEdges": [
{
"from": "lib-skill:fpga-programming--synthesis-optimization",
"to": "skill-area:hdl-design",
"kind": "lib_requires_skill_area",
"attributes": {
"weight": 1
}
},
{
"from": "lib-skill:fpga-programming--synthesis-optimization",
"to": "skill-area:fpga-synthesis",
"kind": "lib_requires_skill_area",
"attributes": {
"weight": 0.7
}
},
{
"from": "lib-skill:fpga-programming--synthesis-optimization",
"to": "domain:embedded-systems",
"kind": "lib_applies_to_domain",
"attributes": {
"weight": 1
}
},
{
"from": "lib-skill:fpga-programming--synthesis-optimization",
"to": "role:embedded-engineer",
"kind": "lib_involves_role",
"attributes": {
"weight": 1
}
},
{
"from": "lib-skill:fpga-programming--synthesis-optimization",
"to": "specialization:fpga-programming",
"kind": "lib_belongs_to_specialization",
"attributes": {
"weight": 1
}
}
],
"incomingEdges": []
}