II.
LibrarySkill JSON
Structured · livelib-skill:fpga-programming--hls-cpp-to-rtl
hls-cpp-to-rtl json
Inspect the normalized record payload exactly as the atlas UI reads it.
{
"id": "lib-skill:fpga-programming--hls-cpp-to-rtl",
"_kind": "LibrarySkill",
"_file": "generated-library/skills.yaml",
"_cluster": "generated-library",
"attributes": {
"displayName": "hls-cpp-to-rtl",
"description": "Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools",
"libraryPath": "library/specializations/fpga-programming/skills/hls-cpp-to-rtl/SKILL.md",
"specialization": "fpga-programming",
"contentSummary": "# HLS C/C++ to RTL Skill\n\n## Overview\n\nExpert skill for High-Level Synthesis (HLS) development, converting C/C++ algorithms to optimized RTL implementations for FPGA acceleration.\n\n## Capabilities\n\n- Write HLS-synthesizable C/C++ code\n- Apply Vitis HLS pragmas (PIPELINE, UNROLL, ARRAY_PARTITION)\n- O"
},
"outgoingEdges": [
{
"from": "lib-skill:fpga-programming--hls-cpp-to-rtl",
"to": "skill-area:hdl-design",
"kind": "lib_requires_skill_area",
"attributes": {
"weight": 1
}
},
{
"from": "lib-skill:fpga-programming--hls-cpp-to-rtl",
"to": "skill-area:fpga-synthesis",
"kind": "lib_requires_skill_area",
"attributes": {
"weight": 0.7
}
},
{
"from": "lib-skill:fpga-programming--hls-cpp-to-rtl",
"to": "domain:embedded-systems",
"kind": "lib_applies_to_domain",
"attributes": {
"weight": 1
}
},
{
"from": "lib-skill:fpga-programming--hls-cpp-to-rtl",
"to": "role:embedded-engineer",
"kind": "lib_involves_role",
"attributes": {
"weight": 1
}
},
{
"from": "lib-skill:fpga-programming--hls-cpp-to-rtl",
"to": "specialization:fpga-programming",
"kind": "lib_belongs_to_specialization",
"attributes": {
"weight": 1
}
}
],
"incomingEdges": []
}