{
  "id": "lib-process:fpga-programming--memory-interface-design",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/memory-interface-design",
    "description": "Memory Interface Design - Design high-performance memory interfaces including DDR3/DDR4 controllers,\nSRAM interfaces, and on-chip memory architectures. Optimize for bandwidth, latency, and power.",
    "libraryPath": "library/specializations/fpga-programming/memory-interface-design.js",
    "specialization": "fpga-programming",
    "references": [
      "- JEDEC DDR4 Standard: https://www.jedec.org/standards-documents/docs/jesd79-4",
      "- Xilinx MIG: https://docs.amd.com/r/en-US/ug586_7Series_MIS",
      "- Intel EMIF: https://www.intel.com/content/www/us/en/programmable/documentation/bhc1410334853449.html"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/memory-interface-design', {\n  designName: 'video_frame_buffer',\n  memoryType: 'DDR4',\n  dataWidth: 64,\n  addressWidth: 32,\n  clockFrequency: 800\n});",
    "usesAgents": [
      "memory-engineer",
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--memory-interface-design",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--memory-interface-design",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--memory-interface-design",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--memory-interface-design",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--memory-interface-design",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--memory-interface-design",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}