{
  "id": "lib-process:fpga-programming--hardware-software-codesign",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/hardware-software-codesign",
    "description": "Hardware-Software Co-Design - Partition algorithms between PS (Processing System) and PL (Programmable Logic).\nDesign hardware accelerators with software drivers and optimize system-level performance.",
    "libraryPath": "library/specializations/fpga-programming/hardware-software-codesign.js",
    "specialization": "fpga-programming",
    "references": [
      "- Zynq UltraScale+ Guide: https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm",
      "- Vitis Unified Platform: https://docs.amd.com/r/en-US/ug1393-vitis-application-acceleration",
      "- Intel SoC FPGA: https://www.intel.com/content/www/us/en/products/details/fpga/soc.html"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/hardware-software-codesign', {\n  designName: 'image_processing_soc',\n  targetPlatform: 'Zynq UltraScale+ MPSoC',\n  algorithmSpec: { name: 'image_filter', operations: ['convolution', 'resize', 'color_convert'] },\n  partitionStrategy: 'performance_optimized'\n});",
    "usesAgents": [
      "system-architect",
      "fpga-engineer",
      "embedded-engineer",
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--hardware-software-codesign",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--hardware-software-codesign",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--hardware-software-codesign",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--hardware-software-codesign",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--hardware-software-codesign",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--hardware-software-codesign",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}