iiRecord
Agentic AI Atlas · specializations/fpga-programming/functional-simulation
lib-process:fpga-programming--functional-simulationa5c.ai
II.
LibraryProcess JSON

lib-process:fpga-programming--functional-simulation

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specializations/fpga-programming/functional-simulation json

Inspect the normalized record payload exactly as the atlas UI reads it.

File · generated-library/processes.yamlCluster · generated-library
Record JSON
{
  "id": "lib-process:fpga-programming--functional-simulation",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/functional-simulation",
    "description": "Functional Simulation and Debug - Execute functional simulations to verify RTL behavior against\nspecifications. Debug failing tests using waveform analysis and signal tracing.",
    "libraryPath": "library/specializations/fpga-programming/functional-simulation.js",
    "specialization": "fpga-programming",
    "references": [
      "- ModelSim/QuestaSim User Guide: https://eda.sw.siemens.com/en-US/ic/questa/",
      "- VCS User Guide: https://www.synopsys.com/verification/simulation/vcs.html",
      "- Verilator: https://www.veripool.org/verilator/"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/functional-simulation', {\n  designName: 'pcie_controller',\n  testbenchPath: 'tb/pcie_controller_tb.sv',\n  simulator: 'QuestaSim',\n  debugLevel: 'full',\n  waveformFormat: 'fsdb'\n});",
    "usesAgents": [
      "verification-engineer",
      "technical-writer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "workflow:hardware-software-integration",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--functional-simulation",
      "to": "lib-agent:meta--technical-writer",
      "kind": "uses_agent",
      "attributes": {
        "weight": 0.8
      }
    }
  ],
  "incomingEdges": []
}