{
  "id": "lib-process:fpga-programming--axi-interface-design",
  "_kind": "LibraryProcess",
  "_file": "generated-library/processes.yaml",
  "_cluster": "generated-library",
  "attributes": {
    "displayName": "specializations/fpga-programming/axi-interface-design",
    "description": "AXI Interface Design and Implementation - Design AXI4, AXI4-Lite, and AXI4-Stream interfaces. Implement\nmasters, slaves, and interconnect components following ARM AMBA specifications.",
    "libraryPath": "library/specializations/fpga-programming/axi-interface-design.js",
    "specialization": "fpga-programming",
    "references": [
      "- ARM AMBA AXI Protocol: https://developer.arm.com/documentation/ihi0022/latest",
      "- AXI4-Stream Protocol: https://developer.arm.com/documentation/ihi0051/latest",
      "- Xilinx AXI Reference: https://docs.amd.com/r/en-US/ug1037-vivado-axi-reference-guide"
    ],
    "example": "const result = await orchestrate('specializations/fpga-programming/axi-interface-design', {\n  designName: 'dma_controller',\n  axiType: 'AXI4',\n  interfaceRole: 'master',\n  dataWidth: 64,\n  addrWidth: 32\n});",
    "usesAgents": [
      "axi-engineer",
      "verification-engineer"
    ]
  },
  "outgoingEdges": [
    {
      "from": "lib-process:fpga-programming--axi-interface-design",
      "to": "skill-area:hdl-design",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--axi-interface-design",
      "to": "skill-area:fpga-synthesis",
      "kind": "lib_requires_skill_area",
      "attributes": {
        "weight": 0.7
      }
    },
    {
      "from": "lib-process:fpga-programming--axi-interface-design",
      "to": "domain:embedded-systems",
      "kind": "lib_applies_to_domain",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--axi-interface-design",
      "to": "role:embedded-engineer",
      "kind": "lib_involves_role",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--axi-interface-design",
      "to": "workflow:architecture-decision-record",
      "kind": "lib_implements_workflow",
      "attributes": {
        "weight": 1
      }
    },
    {
      "from": "lib-process:fpga-programming--axi-interface-design",
      "to": "specialization:fpga-programming",
      "kind": "lib_belongs_to_specialization",
      "attributes": {
        "weight": 1
      }
    }
  ],
  "incomingEdges": []
}